SystemVerilog - 5 days course
- SV Overview
- SV Conventions and Datatypes
- Assignment Statements, Operators, and Expressions
- Processes & Interprocess Synchronization and Communication
- Modules, Programs, Packages, and Interfaces
- Scheduling Semantics, Constraints, Coverage, and Generate Constructs
- SV Classes
- Tasks and Functions
Unified Verification Methodology (UVM)- 10 days course
- UVM Introduction & Overview
- UVM Components and Tests
- UVM Environments and Connecting Objects
- UVM Transactions and Analysis Layer
- Introduction to UVM Reporting
- Introduction to UVM Sequences
- Architecting a UVM Testbench
- UVM Factory and Configuration
- Creating and Modeling Transactions
- UVM Creation and Execution of Sequences
- Managing Tests
- Functional Coverage
Physical Design - Tool agnostics training
- Logic Synthesis
- Static Timing Analysis
- Chip Planning
- Clock Tree Synthesis
- Place & Route
- IO Design
- SignOff
We work with a passion of taking challenges and creating new ones in the VLSI sector.
We work with a passion of taking challenges and creating new ones in the VLSI sector.
© All Copyright 2024 by Orion VLSI Technologies